1. Field of the Invention
The present invention is related to high-throughput discrete-time systems with parallel pipelined architectures, and more particularly, to high-speed analog front-end circuits, such as time-interleaved analog-to-digital converters and to programmable gain amplifiers that precede the analog-to-digital converters.
2. Related Art
Many modern data communications systems use parallel pipelined architectures in order to increase the data throughput. In essence, this approach utilizes a number of identical pipelined sub-circuits arranged in parallel. Another term for this architecture is “time interleaving.”
FIG. 1A illustrates a conventional time interleaved analog-to-digital converter (ADC). As shown in FIG. 1A, an analog voltage Va is sampled by track-and-hold amplifiers 102A–102P. The track-and-hold amplifiers 102A–102P are clocked by clocks fadcA–fadcP, as shown in the figure. The outputs of the track-and-hold amplifiers 102A–102P are inputted to sub-analog-to-digital converters 104A–104P, and then to encoders 106A–106P. Demultiplexers 108A–108H input the multiple-phase output digital signals representing a digitized version of the input analog voltage Va of the corresponding encoders 106A–106P, and output a number of single-phase digital signals, each at a lower rate.
FIGS. 1B–1C illustrate a generalized phase relationship of conventional parallel pipelined circuits. FIG. 1B shows a conventional pipelined parallel operation of either an analog or a digital circuit. Shown in FIG. 1B are three stages “a”, “b” and “c” of a device, with each stage having 3 sampling devices M (Ma, Mb, Mc), 3 analog or digital circuits A (Aa0–Aa2, Ab0–Ab2, Ac0–Ac2), clocked by the clock signals f0–f2 (note that only 3 devices in each stage are shown), with the data outputs sa0–sa2, sb0–sb2, sc0–sc2. Clocked sampling devices Mx are necessary. Common examples of Mx are track-and-hold (T/H) in the analog domain and D flip-flop (DFF) in the digital domain. FIG. 1C shows a relationship between the clock phase and signal phase—in other words, the clock is a multiple phase single rate clock.
The problem with this approach is that the slow running block in the backend limits the system clock frequency. The circuit bandwidth of the Ax blocks naturally reduces from the front-end to the backend as the block functionality increases toward the backend. However, the front-end bandwidth can not be scaled-down to match the slow clock, because the front-end has to track the fast varying signal, and/or the matching or noise (kT/C) requirements may prevent the scaling. The front-end is usually the bottleneck in mismatch and noise because of the signal amplification in the front-end stage.
More granularity in the clock rate is therefore needed to improve the efficiency for a given throughput. Accordingly, there is a need in the art for high bandwidth architectures that utilize an architectural approach to solving the bandwidth problem.